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By Jack Ganssle

The LPC800

Published on, December, 2012.

The press has been somewhat gaga lately over ARM's new Cortex-A50 series of processors, 64 bit monsters that will target the high-end of the spectrum. And they do look great. But to me the more interesting story is the rapid proliferation of ARM Cortex-M series microcontrollers over the last couple of years. NXP, ST, TI, Freescale and others have released hundreds, maybe thousands, of variants with differing peripheral and memory mixes.

Now NXP has gone even lower, with a series of M0+ parts called the LPC800 that sells for $0.39 in volume. Think about that: a 32 bit microcontroller which costs less than a small bag of chips (not the silicon kind). And for the first time that I am aware of, you can get a 32 bitter in an 8 pin package. (Higher-pin-count packages are available, too).

That is pretty cool.

It is being touted as a part with very low power consumption, but at the moment only typ numbers are being published, and while typ is nice to know it's not useful for making serious design decisions. The company tells me they are still working on getting the max values. The typicals indicate a part that is indeed frugal, but one that can't compete with 8 and 16 bit devices like TI's MSP430 and Microchip's XLP series. (Or maybe it can; we won't know till the max numbers are released, but energy use is usually more interesting than raw amps, and a faster part will do more work in less time before going into a deep sleep.)

The part has some unusual and interesting features. For instance, all of the GPIO pins have programmable glitch rejection logic. Any input is invalid unless it remains high for some number of clock cycles (zero is an option).

Then there's the pattern match engine, which, remarkably, doesn't appear to have an associated TLA (three-letter acronym). Using a ton of registers it's possible to create quite complex Boolean expressions whose input terms include up to 8 GPIO pins. Each product term (up to 8 are allowed) can generate a interrupt when true, and the entire expression can itself interrupt the CPU. Or, the result can be dumped onto an output pin, letting one build a bit of custom logic to control part of a system.

Product terms are the usual types of Boolean logic, but can also be the result of edge detection.

(Obviously, one could do this with code as well. However, the pattern match engine runs at logic speeds.)


Eight of these "slices" comprise the LPC800's pattern match engine.

Here's where the glitch rejection shines: the input pins may be sampling real-world ugly signals, but the glitch logic cleans them up before they are processed by the pattern match engine.

The idea is compelling. It's not new; Cypress's PSOC and Microchip's "puddle of gates" are similar. But I think the LPC800 is the first ARM part with such capability. Obviously, I'm ignoring FPGAs which are philosophically different and are in entirely different price ranges.

Other nifty features include a poorly-documented ROM of some sort that contains drivers for the I2C, USART and power profiles, and a timergeddon. The latter is called the state configurable timer, and can be programmed to do just about anything one would want from a timer, counter, event matcher, and the like. I count 113 registers associated with it.

The user's manual is here: . It needs some serious work before it is complete and in some cases comprehensible. The datasheet is here and it, too, is a work in progress.

With this part, and similar ones from other vendors based on the Cortex-M series, especially the M0 and M0+, 32 bits will continue to marginalize 8 and 16 bits. Some of these vendors are very cleverly staking out new territories, like ultra-low power which today ARM can't assail. Another battleground is the mix of peripherals; companies are now offering some quite unusual devices to differentiate their offerings.

The result is great for us, but one wonders where these microcontroller vendors will make money. At $0.39 - and that is just the latest limbo low, surely to be bettered soon - margins must be insanely thin.