Resistors

Published in December, 1994 in EDN.

By Jack Ganssle

When I was a young technician my associates and I arrogantly believed we could build anything with enough 10k resistors and duct tape. Now it seems that even simple electronic toys use several million transistors encased in tiny SMT packages with hundreds of hairlike leads; no one talks about discrete components anymore. Yet no matter how digital our embedded designs get we can never avoid from certain fundamental electrical properties of our circuits.

For example, somehow the digital age has greater an ever-increasing need for resistors - so many, in fact, that most "discrete" resistors are now usually implemented in a monolithic structure, like a SIP, not so different than the ICs they are tied to.

This column is inspired by a system I dug into recently that used a resistor configuration which, while perhaps electrically correct, caused no end of problems for the user. Too often we spend our time carefully analyzing the best way to use a modern miracle of integration only to casually select discrete components because they are, well, boring. Who can get worked up over the lowly carbon resistor? You can't even buy them one at a time any more. At Radio Shack they come paired in bright decorator packages for an outrageous sum. Through Digi-Key the price is right but you must buy 100 at a shot.

The system that got my dander up was reasonably designed. Based on an 8 Mhz 80188, memory and I/O were all connected in a carefully thought out manner. Power and ground distribution were well planned; noise levels were satisfyingly low. And yet... the only tool that seemed to work for debugging code was a logic analyzer. Every emulator the poor designer tested failed to run the code properly. Even a ROM emulator gave erratic results.

Though the emulator wouldn't run the user's code, it did show an immediate service of the non-maskable interrupt - which wasn't used in the system. A little further investigation revealed that the NMI input (which is active high on the 188) was tied low through a 47k resistor.

Now, the system ran fine with a ROM and processor on the board. I suppose the 47k pulldown was at least technically legitimate. A few microamps of leakage current out of the input pin through 47k yields a nice legal logic zero. Yet this 47k was too much resistance when any sort of tool was installed, due to the inevitable increase in leakage current.

Was the design correct because it violated none of Intel's design specs? I maintain that the specs are just the starting point of good design practice. Never, ever, violate one. Never, ever, assume that simply meeting spec is adequate.

A design is correct only if it reliably satisfies all intended applications - including the first of all applications, debugging hardware and software. If something that, while technically correct, prevents proper debugging, then there is surely a problem.

Pulldown resistors are often a source of trouble. It's practically impossible to pull down an LS input (leakage is so high the resistor value must be frighteningly low). Though CMOS inputs leak little, you must be aware of every potential application of the circuit, including that of plugging tools in. The solution is to avoid pulldowns wherever possible.

In the case of a critical edge-triggered (read "really noise sensitive") input like NMI you simply should never pull it low. Tie it to ground. Otherwise switching noise may get coupled into the input. Even worse, every time you lay out the PC board the magnitude of the noise problem can change as the tracks move around the board.

Be conservative in your designs, especially when a conservative approach has no downside. If any input must be zero all of the time, simply tie it to ground and never again worry about it. I think folks are so used to adding pullups all over their boards that they design in pulldowns through the force of habit.

Once in a while the logic may indeed need a pulldown to deal with unusual I/O bits. Try to come up with a better design

Resistor Values

Though pulldowns are always problematic, well designed boards use plenty of pull up resistors - some to bias unused inputs, others to deal with signals and busses that tristate, and some to put switches and other inputs into known one states.

The biggest problem I see with pullups is using values that are too low. A 100k pull-up will in fact bias that CMOS gate properly, but creates a circuit with a terribly high impedance. Why not change to 10k? You buy an order of magnitude improvement in impedance and noise immunity, yet typically use no additional current since the gate requires only microamps of bias.

Vcc from a decent power supply is essentially a low impedance connection to ground. Connect a 100k pull-up to a CMOS gate and the input is 100k away from ground, power, and everything else - you can overcome a 100k resistance by touching the net with a finger. A 10k resistor will overpower any sort of leakage created by fingers, humidity and other effects.

state no matter what tools you use. In the case of NMI from the example above, the tools weakly pulled NMI high so they can run standalone (without the target); the 47k resistor was too high a value to overcome this slight amount of bias.

If you are pulling up a signal from off-board, by all means use a very low value of resistance. The pull-up can act as a termination as well as a provider of a logic one, but the characteristic impedance of any cable is usually on the order of hundreds of ohms. A 100k pull-up is just too high to provide any sort of termination, leaving the input subject to cross coupling and noise from other sources.A1k resistor will help eliminate transients and crosstalk.

Remember as well that you may not have a good idea what the capacitance of the wiring and other connections will be. A strong pull-up will reduce capacitive time constant effects.

Unused Inputs

Once upon a time, back before CMOS logic was so prevalent, you could often leave unused inputs dangling unconnected and reasonably expect to get a logic one. Still, engineers are a conservative lot, and most were careful to tie these spare pins to logic one or zero conditions.

But what exactly is a logic one? With LS logic it's unwise to use Vcc as an input to any gate. Most LS devices will happily tolerate up to 7 volts on Vcc before something fails, while the input pins have an absolute maximum rating of around 5.5 volts. Connecting an input to Vcc creates a circuit where small power glitches that the devices can tolerate may blow input transistors. It's far better to connect the input to Vcc through a resistor, thus limiting input current and yielding a more power-tolerant design.

Modern CMOS logic in most of its guises have the same absolute maximum rating for Vcc as for the inputs so it's perfectly reasonable to connect input pins directly to Vcc - if you are sure that production will never substitute an LS equivalent for the device you've called out.

CMOS does require that every unused input be pulled to a valid logic zero or one to avoid generating an SCR latchup condition.

Fast CMOS logic (like FCT) switches so quickly, even at very low clock rates, that glitches with Fourier components into the gigahertz are not uncommon. Reduce noise susceptibility by tying your logic zeroes and ones directly to the power and ground planes. Avoid pullups and pulldowns - they add parts and reduce reliability.

And yet... one must balance the rules of good design with practical ways to make a debuggable system. A thousand years ago circuits used vacuum tubes mounted on a metal chassis. All connections were made by point-to-point wiring; so making engineering changes during prototype checkout must have been pretty easy. Later, transistors and ICs lived on PC boards but incorporating modifications was still pretty simple. Now we're faced with whisker- thin leads on surface mount components, with 8 and 10 layer boards where most tracks are buried under layers of epoxy and out of reach of our X-Acto knives. If we tie every unused input, even on our spare gates, to a solid power or ground connection, it'll be awfully hard to cut the connection free to tie it somewhere else. Lifting the pins on those spare gates might be a nightmare.

It seems the solution is to build the prototype boards a little differently than the production versions. I look at a design and try to identify areas most likely to require cutting and pasting during checkout. A prime example is the programmable device - PALs or FPGAs or whatever. Bitter experience has taught me that probably I'll forget a crucial input to that PAL, or that I'll need to generate some nastily complex waveform using a spare output on the FPGA.

Some engineers figure if they socket the programmable logic they can lift pins and tack wires to the dangling input or output. I hate this solution. Sometimes it takes and embarrassing number of tries to get a complex PAL right - each time you must remove the device, bend the leads back to program it, and then reinstall the mods. (An alternative is to put a socket in the socket, and lift the upper socket's leads). When the device is PLCC or other, non-DIP package, it's even harder to get access to the pins.

So I leave all unused inputs on these devices unconnected when building the prototype, unfortunately creating a window of vulnerability to SCR latchup conditions. Then it's easy to connect mod wires to the unconnected pins. When the first prototype is done I'll change the schematic to properly tie off the unused inputs so prototype 2 (or the production units) are designed correctly.

In years of doing this I have never suffered a problem from SCR latchup due to these dangling pins. The risk is always there, lurking and waiting for an unusual ESD or perhaps even a careless ungrounded finger biasing an input.

I do tie spare gate inputs to ground, even with the first run of boards. It just feels a little too dangerous to leave an unconnected 74HC74 lead dangling. However, if at all possible, I have the person doing the PCB layout connect these grounds on the bottom layer so that a few quick strokes of the X-Acto knife can free them to solve another "whoops".

This does bring up another important point - I feel the days of wire wrap prototypes are dead. Modern logic is simply too fast to support anything but the best quality multilayer PCBs (with solid ground and power planes) even during prototyping. It's cheap to get 2 copies of a prototype PCB built quickly - look in the little ads in the back of this magazine for sources of quick turn boards. By planning for disposable prototype PCBs one can eliminate all sources of untraceable weirdness from a noisy prototype, and one can easily make small changes to the design just for the sake of increasing the product's debuggability.

In designs that use through-hole parts, by all means leave just a little extra room around each chip so you can socket the parts on the prototype. It's a lot easier to pull a connected pin from a socket than to cut it free from the board.

I want to leave you with three thoughts:

1. Avoid pull down resistors at all costs!
2. Don't be afraid to use low resistor values even in CMOS circuits. A static pull-up needs only microamps no matter what resistor value is selected.
3. Sometimes we spend far more time troubleshooting our designs than actually drawing schematics. Lay out the prototypes in an easy-to-debug form; change them in production.

 

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